- 2 to 6 years of experience in Layout for Custom or Compiled Memories/SRAMs
- Should have extensive experience in 28nm and below technology and MUST have 1 year of experience with FinFets designs (14nm/10nm/7nm)
- The role will involve working on floorplan, layout and physical verification of leaf cells and blocks.
- Applicants must be good team players. Experience with Serial Link applications will be a plus.
- Skill Programming will be added advantage.
- Proficient with Cadence, Synopsys and Mentor design tools- Layout and Verification.
- Qualification- Bachelors or Masters in Engineering.
Bachelors or Masters in Engineering.
2 to 6 years of experience in Layout for Custom or Compiled Memories/SRAMs