Jobs


Front End Modeling Engineer

  • Development of EDA views for Memories Verilog Behavioral model
  • VHDL RTL model
  • Liberty Timing Model
  • Verilog Testbench
  • DFT views like Tetramax & Fastscan
  • Should have good understanding of EDA views  & flows
  • Should know scripting using Tcl/perl
Location: 
Bangalore
Job Type: 
Full Time
Department: 
Semiconductor
Qualification: 
Bachelors or Masters in Engineering.
Specific Requirement: 
EDA views for Memories Verilog Behavioral model, VHDL RTL mode,Liberty Timing Model etc