Jobs


Design Verification Engineer (Job Code: FEV)

 

  • Total Experience of 3-9 Yrs with in-depth knowledge/experience of System Verilog OVM/UVM.
  • Experience & good understanding of ASIC/SoC pre-silicon verification concept i.e. focus vs full/constraint random testing, coverage based verification, testbenching, ip vs fullchip testing.
  • Experience in coverage points coding, SV test writing & debug, test-benching. Exposure to EDA simulation tools i.e. Modelsim/Questasim/VCS/NCsim or debug tools i.e. Verdi/ Debussy.
  • Qualification- Bachelors or Masters in Engineering.
Location: 
Bangalore
Job Type: 
Full Time
Department: 
Semiconductor
Qualification: 
Bachelors or Masters in Engineering.
Specific Requirement: 
Experience of 3-9 Yrs with in-depth knowledge/experience of System Verilog OVM/UVM