[DV] Design Verification Engineer


Right candidate for this position should be proficient in below activities & skills with total relevant experience of 5 to 10 years.

  • Exceptional Digital fundamentals
  • Hands on experience in System Verilog successfully executing multiple products
  • Hands on experience in OVM / UVM Verification
  • Good in GLS
  • Automation
  • Hands on experience in industry standard Verification flows
  • Developing Verification/Test Plans
  • Worked on CDV [Coverage Driven Verification]
  • Writing Functional Coverage
  • Writing SVA [Assertions]
  • Scoreboard development
  • RAL [usage] for Register Coverage
  • Developing automation flows using make, c-shell¬† and perl scripts
  • Scripting and managing regression flows

POSITION: Based on experience and expertise