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|SNO||Job Title||Department||Specific Requirement||Apply Now|
|1||Analog Layout (Job Code: ALE)||Semiconductor||3 to 6 years of experience in Layout for Analog IPs ...||Read & Apply|
|2||Physical Design Engineer (Job Code: PDE)||Semiconductor||4 to 10 years experience in P&R from RTL to GDS including timing closure and Physical verification....||Read & Apply|
|3||Design Verification Engineer (Job Code: FEV)||Semiconductor||Experience of 3-9 Yrs with in-depth knowledge/experience of System Verilog OVM/UVM...||Read & Apply|
|4||Front End Modeling Engineer||Semiconductor||EDA views for Memories Verilog Behavioral model, VHDL RTL mode,Liberty Timing Model etc...||Read & Apply|
|5||Memory Layout Engineer||Semiconductor||2 to 6 years of experience in Layout for Custom or Compiled Memories/SRAMs...||Read & Apply|
|6||IO & Analog Layout Engineer||Semiconductor||2 to 6 years of experience in Layouts for IOs & Analog Designs ...||Read & Apply|